rx_fifo_clock_mode=wr_apb, rx_fifo_clock_enable=disable, tx_fifo_clock_enable=disable
UART FIFO Clock Control Register
| rx_fifo_clock_enable | 0 (disable): undefined 1 (enable): undefined |
| tx_fifo_clock_enable | 0 (disable): undefined 1 (enable): undefined |
| rx_fifo_clock_mode | 0 (wr_apb): Sync mode, writing/reading clocks use apb clock 1 (w_apb_r_ahb): Sync mode, writing clock uses apb clock, reading clock uses ahb clock |
| fifo_depth |