Allwinner /D1H /UART[1] /FCC

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Interpret as FCC

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)rx_fifo_clock_enable 0 (disable)tx_fifo_clock_enable 0 (wr_apb)rx_fifo_clock_mode 0fifo_depth

tx_fifo_clock_enable=disable, rx_fifo_clock_mode=wr_apb, rx_fifo_clock_enable=disable

Description

UART FIFO Clock Control Register

Fields

rx_fifo_clock_enable

0 (disable): undefined

1 (enable): undefined

tx_fifo_clock_enable

0 (disable): undefined

1 (enable): undefined

rx_fifo_clock_mode

0 (wr_apb): Sync mode, writing/reading clocks use apb clock

1 (w_apb_r_ahb): Sync mode, writing clock uses apb clock, reading clock uses ahb clock

fifo_depth

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